1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated semiconductor devices and the manufacturing of such devices, and, more specifically, to various methods of forming a gate cap layer above a replacement gate structure.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout and a specific flow of process operations. Field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit products. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, is typically comprised of doped source and drain regions that are formed in a semiconducting substrate and are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow between the source region and the drain region.
In modern, ultra-high density integrated circuit products, the channel length of the transistors used in such products, i.e., the lateral spacing between the source region and the drain region, has been steadily decreased in size to enhance the performance of the transistors and the overall functionality of integrated circuit products incorporating such transistors. For example, as channel lengths are decreased, the transistors tend to exhibit higher drive current capabilities and faster switching speeds as compared to earlier generations of transistors. Efforts to reduce the channel length of transistors continue to this day as device designers are under constant pressure to improve the performance of such transistors.
However, the historical and ongoing reduction in channel length of transistors, along with the reduction in size of other features of the transistors, causes certain problems that may at least partially offset the advantages that may be obtained by reduction in the channel length of the device. For example, as the channel length of transistors decreases, the pitch between adjacent transistors likewise decreases, thereby limiting the physical size of conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate between adjacent transistors. Accordingly, the electrical resistance of such conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is correspondingly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements. Additionally, the small spacing between adjacent transistors has made it more challenging to precisely locate and form the conductive contact elements in the proper location on the integrated circuit product. For example, if a conductive contact is misaligned, e.g., if it is partially formed on a source region and an adjacent gate structure, the device may not perform as designed and, in a worst-case scenario, such misalignment may establish a short circuit that may lead to complete device failure.
For many early device technology generations, the gate electrode structures of most transistor elements have been made of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprised of alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in a HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), lanthanum, etc.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. FIGS. 1A-1D is a simplified depiction of one illustrative prior art method for forming an HK/MG replacement gate structure using a gate-last technique. As shown in FIG. 1A, the process includes the formation of a basic transistor structure 100 above a semiconducting substrate 10 in an active area defined by a shallow trench isolation structure 11. At the point of fabrication depicted in FIG. 1A, the device 100 includes a sacrificial or dummy gate insulation layer 12, a dummy or sacrificial gate electrode 14, sidewall spacers 16, a layer of insulating material 17 and source/drain regions 18 formed in the substrate 10. The various components and structures of the device 100 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 12 may be comprised of silicon dioxide, the sacrificial gate electrode 14 may be comprised of polysilicon, the sidewall spacers 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NMOS devices and P-type dopants for PMOS devices) that are implanted into the substrate using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 100 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon germanium that are typically found in high-performance PMOS transistors. At the point of fabrication depicted in FIG. 1A, the various structures of the device 100 have been formed and sequence of steps were performed to remove any materials above the sacrificial gate electrode 14 (such as a protective gate cap layer (not shown) comprised of silicon nitride) so that the sacrificial gate electrode 14 may be removed.
As shown in FIG. 1B, one or more etching processes are performed to remove the sacrificial gate electrode 14 and the sacrificial gate insulation layer 12 to thereby define a gate opening 20 where a replacement gate structure will be subsequently formed. Typically, the sacrificial gate insulation layer 12 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 12 may not be removed in all applications, depending upon the material of construction for the gate insulation layer.
Next, as shown in FIG. 1C, various layers of material that will constitute a replacement gate structure 30 are formed in the gate opening 20. In one illustrative example, the replacement gate structure 30 is comprised of a high-k gate insulation layer 30A, a work-function adjusting layer 30B comprised of a metal (e.g., a layer of titanium nitride) and a bulk metal layer 30C (e.g., aluminum). Ultimately, as shown in FIG. 1D, a chemical mechanical polishing (CMP) process is performed to remove excess portions of the gate insulation layer 30A, the work-function adjusting layer 30B and the bulk metal layer 30C positioned outside of the gate opening 20 to define the replacement gate structure 30.
One important aspect of the replacement gate technique involves the formation of a protective dielectric layer (not shown) above the replacement gate structure 30 after the replacement gate structure 30 is formed. Such a protective layer acts to protect the replacement gate structure 30 in subsequent processing operations, such as the various process operations performed to form conductive contacts to the source/drain regions 18. Protection of the replacement gate structure 30 is even more important as device dimensions continue to shrink and the use of self-aligned contact formation techniques are employed in forming conductive contacts to the transistor 100. One technique that has been employed in the past is to simply form another layer of material above the replacement gate structure 30 using known deposition techniques. However, such techniques involve performing a number of time-consuming processing operations and perhaps require hard-masking and patterning, which is not feasible with current lithographic alignment capabilities. More recently, efforts made to form such a protective layer have included oxidizing, nitriding or fluorinating the metal portions of the replacement gate structure 30. See, for example, US Patent Publication No. 2011/0062501. However, as the gate length of the device 100 is scaled, the proportion of the work function adjusting layer 30B becomes much greater as compared to the other layers that make up the replacement gate structure 30. Forming the metal-containing insulating material by oxidation or nitridation of such a work function adjusting layer 30B comprised of, for example, titanium nitride or tantalum nitride has proven to be difficult. Additionally, there is often a stringent constraint on the allowable temperature of the oxidation or nitridation process, which tends to make the oxidation or nitridation of metals more difficult. With fluorination, it is very difficult to form a sufficiently thick oxide cap layer to protect the underlying replacement gate structure 30.
The present disclosure is directed to various methods of forming a gate cap layer above a replacement gate structure and various devices having such a gate cap layer that may solve, or at least reduce, one or more of the problems identified above.